1. Field of the Invention
The present invention relates to an array substrate, and more particularly, to a method of fabricating an array substrate that includes a thin film transistor having excellent properties.
2. Discussion of the Related Art
As the society has entered in earnest upon an information age, a field of display devices that represent all sorts of electrical signals as visual images has developed rapidly. Particularly, the liquid crystal display (LCD) device or the OELD device as a flat panel display device having characteristics of light weight, thinness and low power consumption is developed to be used as a substitute for a display device of cathode-ray tube type.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
On the other hand, since the OELD device has excellent characteristics of high brightness, a low power consumption and high contrast ratio, the OELD device has been widely used. Moreover, the OELD device has advantages of a high response rate, a low production cost and so on.
Both the LCD device and the OELD device require an array substrate including a thin film transistor (TFT) as a switching element for controlling on and off of each pixel region. In addition, the OELD device requires another TFT as a driving element for driving an organic electroluminescent diode in each pixel region. For example, in the LCD device, the TFT as a switching element is connected to a gate line and a data line. The TFT is controlled to provide a signal into a pixel region.
FIG. 1 is a cross-sectional view of a portion of the related art array substrate. In FIG. 1, the array substrate includes a substrate 1 including a pixel region P and the switching region TrA in the pixel region P. On the substrate 1, a gate electrode 3 is disposed in the switching region TrA, and a gate insulating layer 6 covers the gate electrode 3. A semiconductor layer 10 including an active layer 10a and an ohmic contact layer 10b is disposed on the gate insulating layer 6 and in the switching region TrA. The active layer 10a is formed of intrinsic amorphous silicon, and the ohmic contact layer 10b is formed of impurity-doped amorphous silicon. A source electrode 13 and a drain electrode 16, which are spaced apart from each other, are disposed on the semiconductor layer 10. A portion of the ohmic contact layer 10b corresponding to a space between the source and drain electrodes 13 and 16 is removed such that a center of the active layer 10a is exposed through the space between the source and drain electrodes 13 and 16. The gate electrode 3, the gate insulating layer 6, the semiconductor layer 10, the source electrode 13 and the drain electrode 16 constitute the TFT Tr.
A passivation layer 20 including a drain contact hole 23 is formed on the TFT Tr. The drain contact hole 23 exposes the drain electrode 16 of the TFT Tr. A pixel electrode 26 contacting the drain electrode 16 of the TFT Tr is formed on the passivation layer 20 and in each pixel region P.
Although not shown, a gate line, which is connected to the gate electrode 3, is disposed at the same layer as the gate electrode 3. In addition, a data line, which is connected to the source electrode 13, is disposed at the same layer as the source electrode 13.
The active layer in the related art array substrate in FIG. 1 is formed of intrinsic amorphous silicon. Since atoms of intrinsic amorphous silicon are randomly arranged, they have a metastable state when light is irradiated or an electric field is applied. Accordingly, there is an disadvantage in a use for a switching element or a driving element. In addition, the active layer of intrinsic amorphous silicon has a relatively low carrier mobility, for example, 0.1 to 1.0 cm2/V·s, there is further limitation in a use for a driving element.
To resolve these problems, a fabricating method for the TFT including an active layer of plycrystalline silicon has been introduced. Intrinsic amorphous silicon is crystallized into polycrystalline silicon using an eximer laser annealing (ELA) method.
FIG. 2 is a cross-sectional view of the related art array substrate including the active layer of polycrystalline silicon. Referring to FIG. 2, a TFT Tr, a passivation layer 55 including a drain contact hole 56 exposing a portion of the TFT Tr and a pixel electrode 58 are formed on a substrate 30. The TFT Tr includes a semiconductor layer 35, which includes an active region 35a, a source region 35b at one side of the active region 35a and a drain region 35c at the other side of the active region 35a, a gate insulating layer 38, a gate electrode 39, an interlayer insulating layer, which includes a first contact hole 43 for exposing the source region 35b and a second contact hole 44 for exposing the drain region 35c, a source electrode 50 contacting the source region 35b through the first contact hole 43 and a drain electrode 52 contacting the drain region 35c through the second contact hole 44.
Since high impurities should be doped into the source and drain regions 35b and 35c of the semiconductor layer 35, the fabricating method for the array substrate requires an ion implantation apparatus for the doping process. Accordingly, production costs are increased. In addition, since the TFT in FIG. 2 has more complicated structure, production yield is reduced.